1. Field of the Invention
The present invention relates to a semiconductor device in which a silicide technology is unnecessary and to a manufacturing method of the same.
2. Description of the Related Art
Recently, a silicide technology is applied to a transistor in order to reduce resistance, but a cost increases when the silicide technology is applied. Therefore, a silicide layer is not formed in a transistor in which reduction of resistance is not particularly required. As such a transistor, there can be cited, for example, a transistor constituting a memory cell array.
Here, a conventional semiconductor device will be described. FIG. 4 is a cross-sectional view showing the conventional semiconductor device. An element isolation insulating film 102 is formed on a surface of a substrate 101, and two field-effect transistors are formed in an element region defined by the element isolation insulating film 102. In each of the transistors, a tunnel insulating film 103, a floating gate 104, an insulating film 105, a control gate 106, a sidewall 107, a source diffusion layer 141, and a drain diffusion layer 142 are formed. Additionally, an interlayer insulating film 110 covering the transistors is formed. In the interlayer insulating film 110, there are formed a contact hole reaching the source diffusion layer 141 and contact holes reaching the drain diffusion layers 142, and in those contact holes contact plugs 114 are formed. On the interlayer insulating film 110, wirings 115 contacting the contact plugs 114 are formed. Other interlayer insulating films, wirings and the like are formed (not shown) on the wirings 115 and the like. Incidentally, the source diffusion layer 141 of each transistor is shared by the respective transistors.
As described above, a transistor in which a silicide layer is not formed has been conventionally used as the transistor constituting the memory cell array in view of the cost and the like. However, recently, faster operation and reduced driving voltage are required in such a transistor.
Related arts are disclosed in Japanese Patent Application Laid-open No. 2003-197739, Japanese Patent Application Laid-open No. 2000-195950, Japanese Patent Application Laid-open No. Hei 9-148434, Japanese Patent Application Laid-open No. Hei 10-50835, and Japanese Patent Application Laid-open No. Hei 8-274066.